1. Field of the Invention
This invention relates to photoelectric converters and, more particularly, to a photoelectric converter, which comprises a plurality of photoelectric conversion elements capable of storing photoelectrically produced charge. More specifically, the invention concerns a photoelectric converter, which can be suitably used for passive focus detectors for optical apparatuses such as cameras, slide projectors and liquid crystal projectors.
2. Related Background Art
Heretofore, a photoelectric converter of the above type has been proposed by the applicant and disclosed in Japanese Patent Laid-Open Application No. 1-222583.
FIG. 14 shows an equivalent circuit diagram of a photoelectric conversion element array shown in Japanese Patent Laid-Open Application No. 1-222583.
Referring to FIG. 14, designated at 1-1 to 1-n are phototransistors (or cells) of storage type. These phototransistors have such a structure that their collector is connected to a common power supply, and they can store photoelectrically produced charge in their control electrode area (i.e., base) and let stored charge be read out from their main electrode area (i.e., emitter). The structure is described in detail in Japanese Patent Laid-Open Application No. 62-128678, Japanese Patent Laid-Open Application No. 62-113468, Japanese Patent Laid-Open Application No. 63-24664, Japanese Patent Laid-Open Application No. 63-76476 and Japanese Patent Laid-Open Application No. 63-76582. Designated at 2-1 to 2-n are POMS switches for resetting the bipolar transistors of phototransistor array 1 by connecting the bases thereof to power supply V.sub.c when .phi..sub.res is given, at 3-1 to 3-n are NMOS switches each connected to the emitter of each bipolar transistor for taking out stored signal to the following stage in synchronism to .phi..sub.t, at 4-1 to 4-n NMOS switches each connected in series with each of NMOS switches 3-1 to 3-n for sending out image signal to read line 7, and at 5-1 to 5-n are storage capacitors each for reading out signal for each of pixels connected between points of connection between NMOS switches 3-1 to 3-n and 4-1 to 4-n and ground. Designated at 6 is a shift register for reading out image signal by sequentially turning on NMOS switches 4-1 to 4-n, 8 a NMOS switch for connecting read line 7, to which output terminals of NMOS switches 4-1 to 4-n are commonly connected, to ground for initialization when signal .phi..sub.nrs is given, and at 9 is an output amplifier for amplifying image signal output to read line 7. Designated at 10-1 to 10-n are NMOS switches for grounding the emitter of each of phototransistors 1-1 to 1-n when .phi..sub.vrs is given. Designated at 107 is a maximum/minimum value detection circuit, which includes maximum value detection circuits 11-1 to 11-n, minimum value detection circuits 12-1 to 12-n and output amplifiers 13 and 14.
FIG. 15 shows the structure of one minimum value detection circuit.
As shown in FIG. 15, one minimum value detection circuit is constituted by a single differential amplifier 30 and a single pnp transistor 31. Differential amplifier 30 is constituted by constant current circuit 411, PMOS transistors 407 and 408 and NMOS transistors 409 and 410. The emitter line of pnp transistor 31 is fed back to inversion input terminal In2 of differential amplifier 30, and to non-inversion input terminal In1 thereof is connected each emitter of the pixel array of phototransistors 1-1 to 1-n. When the level of non-inversion input In1 of differential amplifier 30 exceeds the level of inversion input In2, the base potential on pnp transistor 31 is changed substantially to the power supply voltage level to turn off pnp transistor 31. In consequence, no voltage is provided as input to output amplifier 13 shown in FIG. 14. When the lowest level voltage is supplied as non-inversion input In1 to differential amplifier 30, pnp transistor 31 produces an output voltage, which is indicative of detection of the minimum value.
FIG. 16 shows the structure of one maximum value detection circuit.
As shown in FIG. 16, one maximum value detection circuit is constituted by a single differential amplifier 32 and a single npn transistor 33. Differential amplifier 32 is constituted by constant current circuit 401, PMOS transistors 402 and 403 and NMOS transistors 404 and 405. The emitter line of npn transistor 33 is fed back to inversion input terminal In2 of differential amplifier 32 and also to an output line. To non-inversion input terminal In1 is connected each emitter of each pixel row. When non-inversion input In1 of differential amplifier 32 becomes lower in level than inversion input In2, the base potential on npn transistor 33 is lowered substantially to the voltage level of negative power supply, thus turning off npn transistor 33. When the highest voltage is supplied as non-inversion input In1 to differential amplifier 32, npn transistor 33 produces an output voltage, which is indicative of detection of the maximum value. In both minimum and maximum value detection circuit, load resistance is denoted by R.
FIG. 17 is a timing chart for explaining the operation of the photoelectric conversion element array shown in FIG. 14.
In the first place, resetting is done. Then, .phi..sub.res is held at low level for a period from instant t.sub.1 to instant t.sub.2, thus turning on PMOS switches 2-1 to 2-n to fix the base potential on phototransistors 1-1 to 1-n of the array (hereinafter referred to pixel row) to V.sub.c.
Subsequently, .phi..sub.vrs and .phi..sub.t are held at high level (i.e., "on") from instant t.sub.3 to instant t.sub.4, thus turning on NMOS switches 10-1 to 10-n and 3-1 to 3-n to ground storage capacitors 5-1 to 5-n and reset residual charge. When the resetting with respect to the bases and emitters of pixel row 1-1 to 1-n is ended, storage operation sets in.
When the storage operation sets in, photoelectrically produced charge is stored in base areas of pixel row 1-1 to 1-n. At this time, the bases and emitters of the pixel row are floating (i.e., in capacitive load state), and a voltage reflecting base potential is present at the emitters.
For sequential reading of signal, NMOS switches 4-1 to 4-n are sequentially turned on by shift register 6, thus reading out signal charges stored in storage capacitors 5-1 to 5-n to read line 7. Shift register 6 selects NMOS switches 4-1 to 4-n one by one each time when .phi..sub.ck is given. Right before selection NMOS switches 4-1 to 4-n, NMOS switch 8 is turned on under control of .phi..sub.nrs to reset charge remaining on read line 7.
Japanese Patent Laid-Open Application No. 1-222583 proposes a method of performing A/D conversion of only featuring portions of an object pattern through storage time control such as to make constant the difference between bright and dark portions of the pattern by constructing a photoelectric converter as shown in FIGS. 8 and 9 with a photoelectric conversion element array provided with maximum and minimum value detection circuits as noted above.
In this method, a check as to whether storage is performed up to an adequate level is done through a check as to whether reference level V.sub.ref is reached by the difference between maximum and minimum values of storage level of the photoelectric conversion element array. Designated at 102 is a differential amplifier for taking the difference between V.sub.max and V.sub.min, and 103 is a comparator for comparing the output of differential amplifier 102 to predetermined reference level V.sub.ref to determine the reaching of adequate storage level. When signal .phi..sub.comp of comparator 103 is inverted, microcomputer 104 detects the reaching of the reference level of storage and provides pulse .phi..sub.t indicative of the ending of storage to photoelectric conversion element array 101. At the same time, it provides signal SH to memory circuit 105 for memorization of level of V.sub.min at the end of storage. Then, .phi..sub.ck and .phi..sub.nrs are provided as read pulses, whereby video signal from photoelectric conversion element is read out for A/D conversion.
In the example of FIG. 8, the A/D conversion range is subject to level shift according to the range of video signal. In the example of FIG. 9, video signal is subject to level shift according to A/D conversion range. In either case, A/D conversion is effected between the maximum and minimum values of video signal.
The digitalized pixel signal which is obtained in the above way is used for focus judgement through calculation as disclosed in Japanese Patent Laid-Open Application No. 58-142306, Japanese Patent Laid-Open Application No. 59-107313, Japanese Patent Laid-Open Application No. 60-101513 or Japanese Patent Laid-Open Application No. 61-18314 (which corresponds to U.S. Pat. No. 4,812,869).
However, with the above prior art photoelectric converter actual maximum and minimum values of pixel signal and values of V.sub.max and V.sub.min are subject to deviation due to such causes different read-out gains of different reading circuits, through which the maximum and minimum values of video signal and photoelectric conversion element array storage signal are provided, and also to mismatching of amplifiers 9, 13 and 14. In addition, where stored charge control is effected according to the difference between V.sub.max and V.sub.min as in the examples of FIGS. 11 and 12, the video signal is liable to partially exceed the A/D conversion range.
The read-out gain difference is produced in the following way. Denoting the capacitance of storage capacitor 5-1 and parasitic capacitance of read line 7 in FIG. 4 by C.sub.T1 and C.sub.H, respectively, the output obtained when emitter potential V.sub.E1 of phototransistor 1-1 is read out to line 7 is ##EQU1## and the gain is not unity.
Nevertheless, the outputs of V.sub.min and V.sub.max are read output with unity gain. Consequently, deviations are produced. To solve this problem, the applicant has proposed a photoelectric converter as disclosed in Japanese Patent Application No. 3-163972.
However, according to Japanese Patent Application No. 1-301818 the following problem is presented, which is desired to be improved.
With a structure where the maximum and minimum values are detected and provided to the same line as the video signal, unless satisfactory balance is obtained between a bus leading from photoreceiving element through read circuit to common output line and a bus leading from maximum/minimum value detection circuit to common output line, the signal-to-noise ratio is reduced, thus resulting in a signal with great fluctuations for individual bits. In such case, it is insufficient to improve the quality of the video signal itself. That is, it is necessary to accurately detect maximum/minimum value data for determining the storage time of photoreceiving element. In addition, it is necessary to let detected maximum/minimum value data be led to the common output line without imparting any noise component.
Particularly, recently two-dimensional photoelectric conversion element array arrangement is desired for photoelectric converters for photo-measurement in order to obtain sensing of object in longitudinal and transversal directions. To obtain such a structure, it may be thought to arrange a plurality of photoelectric converter chips in longitudinal and transversal directions. Adoptation of such structure, however, leads to increased cost of manufacture. In addition, depending on combination, only signal of low signal-to-noise ratio can be obtained.
Particularly, pronounced reduction of the signal-to-noise ratio is liable in case where a digital circuit for generating a clock signal or the like for driving a corresponding photoelectric conversion element array is disposed near a photoreceiving element array section of a different photoelectric conversion element array. A significant cause of this is the introduction of noise component from the digital circuit into the photoelectrically produced signal.
Further, where a photoelectric conversion element array located at an end of a chip containing a plurality of photoelectric conversion element arrays is arranged such that its photoreceiving element section is on the inner side while its read circuit section is on the outer side, the photoreceiving element section is affected by the inner adjacent photoelectric conversion element array in the remaining arrays, leading to failure of accurate reading of signal.